module RegIfId (
    
    pc_in,
    instr_in,
    pc_out,
    instr_out,
    clk
);
    input clk;
    input [31:0] pc_in;
    input [31:0] instr_in;
    output reg [31:0] pc_out;
    output reg [31:0] instr_out;
    always @(posedge clk) begin
        instr_out <= instr_in;
        pc_out <= pc_in;
    end
endmodule //ref_if_id